XOR signal in verilog

XOR signal in verilog

There are a couple of ways of doing this. One way could be to build a 4-input XOR module, and then instantiate multiple copies.

module myXOR4 ( input a, input b, input c, input d, output f);
    assign f = a ^ b ^ c ^ d; // ^ is the XOR operator
endmodule
// ...

myXOR4 xor1 (A[0],A[1],A[2],A[3],out[0]);
myXOR4 xor2 (A[4],A[5],A[6],A[7],out[1]);
// etc

Another way would be to use a for-loop. This wont work with all the cases, since you dont have an evenly-divisible number of wires.

reg [4:0] out;
integer i;
[email protected](*) begin
    for (i=0; i<4; i=i+1) 
        out[i]=A[4*i] ^ A[4*i+1] ^ A[4*i+2] ^ A[4*i+3];
    out[4] = A[18] ^ A[17] ^ A[16];
end

There are some other tricks (like 0-padding the upper-bits of A to make it evenly divisible, which makes the loops simpler) but theyll all end up with the same result, so this should be enough to get you started.

XOR signal in verilog

Leave a Reply

Your email address will not be published.